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All About Reset

September 20th, 2006

In verilog, there are two types of reset, synchronous reset and asynchronous reset. In synchronous reset, reset is sampled with respect to clock, whereas in asynchronous reset, reset is not sampled with respect to clock. There are advantages and disadvanteges of using asynchronous reset and they are it requires less gates to implement, does not requires clock to be active always and it is fast. However it suffers from metastability problem.

An asynchronous D Flip Flop:

module dff_async_reset(data,clk,reset,q);
input data, clk, reset;
output q;
reg q;

always @(posedge clk or negedge reset) //for asynchronous
if (~reset) begin
q = 1′b0;
end else begin
q = data;
end

endmodule

A synchronous D Flip Flop:

module dff_sync_reset(data,clk,reset,q);
input data, clk, reset;
output q;
reg q;

always @ (posedge clk)
if (~reset) begin
q = 1′b0;
end else begin
q = data;
end
endmodule

Notice the always block which distinguishes between asynchronous and synchronous reset.

Filed under: Verilog