ADC DAC 2 MSPS Implementation
May 12th, 2009
Implemented ADC DAC 2 MSPS on Virtex II Pro FPGA. This is a 10 times higher in sampling rate compare to the previous post ADC DAC. The sampling rate is 2 MSPS and can go up to 4 MSPS.
So by using System Generator and a verilog blackbox I implemented an FIR high-pass filter and the result is very clean. high_pass_filter_scope_captures
Filed under: Analog Design, Digital Design, Hardware, Project, School
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